1. Field of Invention
The present invention relates to improvements in digital logic circuits, and more particularly to improvements in pulsed static logic circuits, and still more particularly to an improved pulsed static logic circuit that can be scanned for testing purposes.
2. Relevant Background
Flip-flops are a basic building block for digital logic circuits. They are the most common memory element in digital logic design, being used almost exclusively in synthesized designs, and widely used in custom implementations as well. Static logic flip-flops typically comprise Complementary Metal Oxide Silicon (CMOS) technology.
The output (Q) of a typical static logic flip-flop either transitions to a logic high state or a logic low state, or holds the previous output state, depending upon the data input state to the flip-flop and the state of the trigger to the device. Depending upon the configuration of the flip-flop, the device is either rising edge-triggered, or falling edge-triggered. Edge-triggered flip-flops are ubiquitous and allow for a simple clocking scheme. A rising edge-triggered flip-flop reads the state of the data input and then provides that data value at the output of the flip-flop upon the rising edge the synchronizing clock pulse. The output of the flip-flop is held equal to the previous output state at all times other than during the triggering event.
The standard approach to building a flip-flop is to connect two latches, a master and a slave, such that the output of the master latch provides the input to the slave latch. In the case of a rising edge-triggered flip-flop, a clock-low enabled master latch is followed by a clock-high enabled slave latch. A falling edge-triggered flip-flop would have the clock-high enabled master latch followed by a clock-low enabled slave.
The operation of a rising-edge triggered flip-flop is as follows: When the clock is low, data enters the master latch and is stored there. When the clock rises this data traverses to the slave latch and is visible at the output of the flip-flop. Since the rising clock disables the master latch, new data cannot replace the data that is held in the master latch. When the clock returns low, the output state of the slave latch is held constant, while the next data input state is read into the master latch. The process is then repeated.
The edge-triggered flip-flop is stable and requires a short hold-time, where hold time is defined as the amount of time that the data state must be held constant in order to ensure that it be properly written into the flip-flop upon the arrival of the clock state that allows data to be read by the master latch. The hold time is trivially met in most designs. If timing analysis shows that hold time failures are occurring, the problem can be solved by inserting delays into the fast paths of the design. This can be accomplished automatically by modern synthesis tools, generally with no timing penalty.
The principle limitation of the edge-triggered flip-flop is the propagation delay of the device, the time that it takes for the data to traverse through both latches of the flip-flop. The delay of the device is the sum of the “set-up time” and the “clock-to-q time.” Set-up time is conventionally defined as the set-up time period of the master latch where the data is held before being presented to the slave latch, and clock-to-q time is defined as the time period from the triggering event until the time that the data is available at the output of the flip-flop. For deeply pipelined designs in deep sub-micron technologies, the propagation delay of the flip-flop consumes a large part of the total cycle time. The time required for set-up, clock-to-q and skew in the flip-flop can consume a large portion, sometimes approaching 40%, of the total cycle time.
Another approach to flip-flop design is to use a single latch in combination with a pulse generator, such as described in D. Harris, Skew-Tolerant Design, Morgan Kaufmann Publishers Inc., San Francisco, Calif., 2001. The pulse generator is used to generate a short pulse either on the rising or the falling edge of the clock. This pulse allows the latch to be transparent, i.e. able to read the input data, only for a short time period equal to the width of the pulse following the edge transition. While the pulsed latch has decreased propagation delay, it has the disadvantage of having an increased hold time requirement when compared to a conventional flip-flop.
Pulsed flip-flops can also be designed with a domino logic latch, instead of a static latch. Domino logic is a precharged, non-inverting family of CMOS logic that uses multiple clock phases to effect high-speed operation. Domino logic is faster than standard static logic, but it is more difficult to design because of its increased complexity, primarily in the clocking network. Although domino logic gates are faster than static gates, there are some advantages to using static gates. First, in a domino pulsed flip-flop, the AND logic gate of the pulse generator is part of the series of nMOS pull down transistors. In order to ensure acceptable speed, these transistors must be kept large, which leads to increased power dissipation in the clocking circuitry. Another disadvantage of a pulsed domino flip-flop is the requirement of a latch at the output to ensure that the precharge data value is not propagated into the following circuitry. Static logic has reduced power dissipation in comparison to domino logic, and reduced circuit complexity through the use of fewer gates.
Many domino logic flip-flops are designed to incorporate a scan test capability for testing circuit operation. During a scan test, data enters the flip-flop from another flip-flop or the scan test input. This mode is used to load a set of arbitrary data into the flip-flop to test the correct functionality or manufacture of the device. To incorporate scan test capability into a flip-flop, the data input, a scan test enable input, and the scan test input, are typically fed into a multiplexer. The output of the multiplexer ensures that scan testing can only occur when the test enable input is enabled, thereby providing two modes of operation for the flip-flop, a scan test mode and a data mode. When the test mode is disabled the circuit is in data mode, unable to read a scan test input. Therefore, the circuit can only read the data input or the scan test input, but not both simultaneously.
It would be advantageous if a flip-flop were designed that took advantage of the reduced power requirements of a pulsed static latch, the reduced circuit complexity of static logic, and incorporated a scan test capability to test circuit operation.
The present invention combines simple pulsed static latch circuitry with a scan test capability. In the present invention, the pulse generator circuitry is independent the latch gates, and can therefore be made small to reduce power dissipation. This reduction in power dissipation is combined with the fact that static logic gates consume less power than domino logic gates. The present invention also incorporates a scan test input that is independent of the data input, for testing circuit operation. The novel pulse generator of the present invention operates to automatically select the scan test or data mode of operation.